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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
commit608641e23c7f2288810c3f23a1a63790b664f2ab (patch)
tree0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/arch/alpha
parent6e354e82d9395b20f5f148cd545d0666b626e8ac (diff)
downloadgem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/isa.hh7
-rw-r--r--src/arch/alpha/registers.hh10
-rw-r--r--src/arch/alpha/utility.cc1
3 files changed, 17 insertions, 1 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 6a88ee40b..b5964e622 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -114,6 +114,13 @@ namespace AlphaISA
return reg;
}
+ // dummy
+ int
+ flattenVectorIndex(int reg) const
+ {
+ return reg;
+ }
+
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 3fd774cf7..665ea30c7 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -56,6 +56,12 @@ typedef uint64_t MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
+// vector register file entry type
+typedef uint64_t VectorRegElement;
+const int NumVectorRegElements = 0;
+const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
+typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
+
union AnyReg
{
IntReg intreg;
@@ -95,6 +101,7 @@ const int NumFloatArchRegs = 32;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
const int NumCCRegs = 0;
+const int NumVectorRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs =
@@ -106,7 +113,8 @@ enum DependenceTags {
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
FP_Reg_Base = NumIntRegs,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+ Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
+ Misc_Reg_Base = Vector_Reg_Base + NumCCRegs, // NumVectorRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 2dfe00f96..b0a503828 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -73,6 +73,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
+ assert(NumVectorRegs == 0);
// Copy misc. registers
copyMiscRegs(src, dest);