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authorGabe Black <gblack@eecs.umich.edu>2008-02-26 23:38:51 -0500
committerGabe Black <gblack@eecs.umich.edu>2008-02-26 23:38:51 -0500
commit8b4796a367ec21d294f7318343e5bb9d7e07a53e (patch)
tree584199359a9a7aa3c7d842164b677d1a1e94a1f1 /src/arch/alpha
parent7bde0285e50e3903e38dd9e6fd59ea4a98f41079 (diff)
downloadgem5-8b4796a367ec21d294f7318343e5bb9d7e07a53e.tar.xz
TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
Diffstat (limited to 'src/arch/alpha')
-rw-r--r--src/arch/alpha/tlb.cc2
-rw-r--r--src/arch/alpha/tlb.hh10
2 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 2e974effe..77bf5e285 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -58,7 +58,7 @@ bool uncacheBit40 = false;
#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
- : SimObject(p), size(p->size), nlu(0)
+ : BaseTLB(p), size(p->size), nlu(0)
{
table = new TlbEntry[size];
memset(table, 0, sizeof(TlbEntry[size]));
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 69a33f32d..e61ae5c6d 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -44,7 +44,7 @@
#include "params/AlphaDTB.hh"
#include "params/AlphaITB.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
@@ -52,7 +52,7 @@ namespace AlphaISA
{
class TlbEntry;
- class TLB : public SimObject
+ class TLB : public BaseTLB
{
protected:
typedef std::multimap<Addr, int> PageTable;
@@ -79,6 +79,12 @@ namespace AlphaISA
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ assert(asn < (1 << 8));
+ flushAddr(vaddr, asn);
+ }
+
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1