TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.

--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8

2 files changed, 24 insertions, 34 deletions

diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 7d4de902a..20591b357 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -177,25 +177,12 @@ void ItbFault::invoke(ThreadContext * tc)
 void ItbPageFault::invoke(ThreadContext * tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr physaddr;
-    bool success = p->pTable->translate(pc, physaddr);
+    TlbEntry entry;
+    bool success = p->pTable->lookup(pc, entry);
     if(!success) {
         panic("Tried to execute unmapped address %#x.\n", pc);
     } else {
         VAddr vaddr(pc);
-        VAddr paddr(physaddr);
-
-        TlbEntry entry;
-        entry.tag = vaddr.vpn();
-        entry.ppn = paddr.vpn();
-        entry.xre = 15; //This can be read in all modes.
-        entry.xwe = 1; //This can be written only in kernel mode.
-        entry.asn = p->M5_pid; //Address space number.
-        entry.asma = false; //Only match on this ASN.
-        entry.fonr = false; //Don't fault on read.
-        entry.fonw = false; //Don't fault on write.
-        entry.valid = true; //This entry is valid.
-
         tc->getITBPtr()->insert(vaddr.page(), entry);
     }
 }
@@ -203,28 +190,15 @@ void ItbPageFault::invoke(ThreadContext * tc)
 void NDtbMissFault::invoke(ThreadContext * tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr physaddr;
-    bool success = p->pTable->translate(vaddr, physaddr);
+    TlbEntry entry;
+    bool success = p->pTable->lookup(vaddr, entry);
     if(!success) {
         p->checkAndAllocNextPage(vaddr);
-        success = p->pTable->translate(vaddr, physaddr);
+        success = p->pTable->lookup(vaddr, entry);
     }
     if(!success) {
         panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
     } else {
-        VAddr paddr(physaddr);
-
-        TlbEntry entry;
-        entry.tag = vaddr.vpn();
-        entry.ppn = paddr.vpn();
-        entry.xre = 15; //This can be read in all modes.
-        entry.xwe = 15; //This can be written in all modes.
-        entry.asn = p->M5_pid; //Address space number.
-        entry.asma = false; //Only match on this ASN.
-        entry.fonr = false; //Don't fault on read.
-        entry.fonw = false; //Don't fault on write.
-        entry.valid = true; //This entry is valid.
-
         tc->getDTBPtr()->insert(vaddr.page(), entry);
     }
 }
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 4375f24f1..8ce5b4e5d 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -92,10 +92,21 @@ namespace AlphaISA {
     // ITB/DTB table entry
     struct TlbEntry
     {
-        Addr pageStart;
         //Construct an entry that maps to physical address addr.
-        TlbEntry(Addr addr) : pageStart(addr)
-        {}
+        TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
+        {
+            VAddr vaddr(_vaddr);
+            VAddr paddr(_paddr);
+            tag = vaddr.vpn();
+            ppn = paddr.vpn();
+            xre = 15;
+            xwe = 15;
+            asn = _asn;
+            asma = false;
+            fonr = false;
+            fonw = false;
+            valid = true;
+        }
         TlbEntry()
         {}
 
@@ -109,6 +120,11 @@ namespace AlphaISA {
         bool fonw;			// fault on write
         bool valid;			// valid page table entry
 
+        Addr pageStart()
+        {
+            return ppn << PageShift;
+        }
+
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
     };