diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/arch/alpha | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/alpha')
| -rw-r--r-- | src/arch/alpha/ev5.cc | 2 | ||||
| -rw-r--r-- | src/arch/alpha/registers.hh | 2 | ||||
| -rw-r--r-- | src/arch/alpha/remote_gdb.cc | 4 | ||||
| -rw-r--r-- | src/arch/alpha/utility.cc | 4 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 6a5d6afdc..cc0c583f0 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -88,7 +88,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatRegBits(ZeroReg, 0); + cpu->thread->setFloatReg(ZeroReg, 0); } //////////////////////////////////////////////////////////////////////// diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 218390597..07c0beeb3 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -49,7 +49,7 @@ const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; typedef RegVal IntReg; // floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; // control register file contents typedef RegVal MiscReg; diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index f3eafc0fe..9e87f1783 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -220,7 +220,7 @@ RemoteGDB::AlphaGdbRegCache::getRegs(ThreadContext *context) for (int i = 0; i < 32; ++i) #ifdef KGDB_FP_REGS - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); #else r.fpr[i] = 0; #endif @@ -243,7 +243,7 @@ RemoteGDB::AlphaGdbRegCache::setRegs(ThreadContext *context) const #ifdef KGDB_FP_REGS for (int i = 0; i < NumFloatArchRegs; ++i) { - context->setFloatRegBits(i, gdbregs.regs64[i + KGDB_REG_F0]); + context->setFloatReg(i, gdbregs.regs64[i + KGDB_REG_F0]); } #endif context->pcState(r.pc); diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc index de4b4e34d..c03e7b0da 100644 --- a/src/arch/alpha/utility.cc +++ b/src/arch/alpha/utility.cc @@ -48,7 +48,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) const int NumArgumentRegs = 6; if (number < NumArgumentRegs) { if (fp) - return tc->readFloatRegBits(16 + number); + return tc->readFloatReg(16 + number); else return tc->readIntReg(16 + number); } else { @@ -70,7 +70,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); + dest->setFloatReg(i, src->readFloatReg(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); |