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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2013-01-07 13:05:35 -0500
commit0d1ad50326a13a24daed916a069fc9f45775f51d (patch)
tree69402307a753e23fb617538b93ad485f8e5b9598 /src/arch/arm/ArmISA.py
parent3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (diff)
downloadgem5-0d1ad50326a13a24daed916a069fc9f45775f51d.tar.xz
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers. Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.
Diffstat (limited to 'src/arch/arm/ArmISA.py')
-rw-r--r--src/arch/arm/ArmISA.py40
1 files changed, 40 insertions, 0 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index fc291cfc1..55a589c32 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -35,9 +35,49 @@
#
# Authors: Andreas Sandberg
+from m5.params import *
from m5.SimObject import SimObject
class ArmISA(SimObject):
type = 'ArmISA'
cxx_class = 'ArmISA::ISA'
cxx_header = "arch/arm/isa.hh"
+
+ # 0x35 Implementor is '5' from "M5"
+ # 0x0 Variant
+ # 0xf Architecture from CPUID scheme
+ # 0xc00 Primary part number ("c" or higher implies ARM v7)
+ # 0x0 Revision
+ midr = Param.UInt32(0x350fc000, "Main ID Register")
+
+ # See section B4.1.93 - B4.1.94 of the ARM ARM
+ #
+ # !ThumbEE | !Jazelle | Thumb | ARM
+ # Note: ThumbEE is disabled for now since we don't support CP14
+ # config registers and jumping to ThumbEE vectors
+ id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
+ # !Timer | !Virti | !M Profile | !TrustZone | ARMv4
+ id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
+
+ # See section B4.1.89 - B4.1.92 of the ARM ARM
+ # VMSAv7 support
+ id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
+ id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
+ # no HW access | WFI stalling | ISB and DSB |
+ # all TLB maintenance | no Harvard
+ id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
+ # SuperSec | Coherent TLB | Bcast Maint |
+ # BP Maint | Cache Maint Set/way | Cache Maint MVA
+ id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
+
+ # See section B4.1.84 of ARM ARM
+ # All values are latest for ARMv7-A profile
+ id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
+ id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
+ id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
+ id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
+ id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
+ id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
+
+
+ fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")