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authorTuan Ta <qtt2@cornell.edu>2018-03-01 10:32:26 -0500
committerTuan Ta <qtt2@cornell.edu>2018-03-20 00:57:17 +0000
commit212649b01e90b28df6e1a66c1b98a944af5b05a9 (patch)
tree3b67eab863b14ff066a72cb4cbc57ebc2ee082bf /src/arch/arm/ArmISA.py
parent9dc44b4173b72d15fa7ee49d1b196c2d11c84d02 (diff)
downloadgem5-212649b01e90b28df6e1a66c1b98a944af5b05a9.tar.xz
riscv: throw IllegalInstFault when decoding invalid instructions
If an instruction is invalid, some assertions may in the decoder may fail the entire simulation. Instead, we want to raise an IllegalInstFault instead of failing immediately in the decoder if the invalid instruction is being speculatively executed. Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f Reviewed-on: https://gem5-review.googlesource.com/9261 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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