arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli    (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt       (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole           (AArch64 NEON, validation)
Ali Saidi            (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang         (AArch64 Linux support)
Rene De Jong         (AArch64 Linux support, performance opt.)
Matt Horsnell        (AArch64 MP, validation)
Matt Evans           (device models, code integration, validation)
Chris Adeniyi-Jones  (AArch64 syscall-emulation)
Prakash Ramrakhyani  (validation)
Dam Sunwoo           (validation)
Chander Sudanthi     (validation)
Stephan Diestelhorst (validation)
Andreas Hansson      (code integration, performance opt.)
Eric Van Hensbergen  (performance opt.)
Gabe Black

1 files changed, 46 insertions, 12 deletions

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 55a589c32..eaec92f4d 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -34,8 +34,10 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Andreas Sandberg
+#          Giacomo Gabrielli
 
 from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class ArmISA(SimObject):
@@ -43,12 +45,9 @@ class ArmISA(SimObject):
     cxx_class = 'ArmISA::ISA'
     cxx_header = "arch/arm/isa.hh"
 
-    # 0x35 Implementor is '5' from "M5"
-    # 0x0 Variant
-    # 0xf Architecture from CPUID scheme
-    # 0xc00 Primary part number ("c" or higher implies ARM v7)
-    # 0x0 Revision
-    midr = Param.UInt32(0x350fc000, "Main ID Register")
+    system = Param.System(Parent.any, "System this ISA object belongs to")
+
+    midr = Param.UInt32(0x410fc0f0, "MIDR value")
 
     # See section B4.1.93 - B4.1.94 of the ARM ARM
     #
@@ -56,19 +55,19 @@ class ArmISA(SimObject):
     # Note: ThumbEE is disabled for now since we don't support CP14
     # config registers and jumping to ThumbEE vectors
     id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
-    # !Timer | !Virti | !M Profile | !TrustZone | ARMv4
-    id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
+    # !Timer | Virti | !M Profile | TrustZone | ARMv4
+    id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1")
 
     # See section B4.1.89 - B4.1.92 of the ARM ARM
     #  VMSAv7 support
-    id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
+    id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
     id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
     # no HW access | WFI stalling | ISB and DSB |
     # all TLB maintenance | no Harvard
     id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
     # SuperSec | Coherent TLB | Bcast Maint |
     # BP Maint | Cache Maint Set/way | Cache Maint MVA
-    id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
+    id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
 
     # See section B4.1.84 of ARM ARM
     # All values are latest for ARMv7-A profile
@@ -79,5 +78,40 @@ class ArmISA(SimObject):
     id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
     id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
 
+    fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
+
+    # [31:0] is implementation defined
+    id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Auxiliary Feature Register 0")
+    # Reserved for future expansion
+    id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Auxiliary Feature Register 1")
+
+    # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
+    id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
+        "AArch64 Debug Feature Register 0")
+    # Reserved for future expansion
+    id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Debug Feature Register 1")
+
+    # !CRC32 | !SHA2 | !SHA1 | !AES
+    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Instruction Set Attribute Register 0")
+    # Reserved for future expansion
+    id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Instruction Set Attribute Register 1")
+
+    # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
+    id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
+        "AArch64 Memory Model Feature Register 0")
+    # Reserved for future expansion
+    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Memory Model Feature Register 1")
 
-    fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")
+    # !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
+    # (no AArch32/64 interprocessing support for now)
+    id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
+        "AArch64 Processor Feature Register 0")
+    # Reserved for future expansion
+    id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Processor Feature Register 1")