diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
| commit | a73937b60c0057d006938bca7ec69a8b48450f2c (patch) | |
| tree | 5d6a51c05403196104f17617f6e8ae725a19c2bb /src/arch/arm/ArmISA.py | |
| parent | 282cf5807d827d5583e5cd5bffae75c4e5efb116 (diff) | |
| download | gem5-a73937b60c0057d006938bca7ec69a8b48450f2c.tar.xz | |
arm: compute ID_PFR{0,1} registers
Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.
Change-Id: Ie7685b5d8b5f2dd9d6380b4af74f16d596b2bfd1
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/ArmISA.py')
| -rw-r--r-- | src/arch/arm/ArmISA.py | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 146ca6494..fbefe3daf 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -57,15 +57,6 @@ class ArmISA(SimObject): midr = Param.UInt32(0x410fc0f0, "MIDR value") - # See section B4.1.93 - B4.1.94 of the ARM ARM - # - # !ThumbEE | !Jazelle | Thumb | ARM - # Note: ThumbEE is disabled for now since we don't support CP14 - # config registers and jumping to ThumbEE vectors - id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0") - # !Timer | Virti | !M Profile | TrustZone | ARMv4 - id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1") - # See section B4.1.89 - B4.1.92 of the ARM ARM # VMSAv7 support id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0") |