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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-10-16 10:04:01 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-25 22:29:52 +0000 |
| commit | 8e8214da55dc807375662dd3044ffb2ec0a2feed (patch) | |
| tree | 4f474f06da3a58ba4c73a41045147f66ef35cf73 /src/arch/arm/ArmISA.py | |
| parent | 0793149cbbf796649bd87f95e52edcaa02b29916 (diff) | |
| download | gem5-8e8214da55dc807375662dd3044ffb2ec0a2feed.tar.xz | |
arch-arm: default MIDR for Armv8 ISA processors
Software such as Trusted Firmware-A checks the MIDR register
to identify which core model is present in the platform.
The previous default value referred to a Cortex-A15 Armv7-A
processor, however when AArch64 is enabled, an Armv8 processor
is expected.
This patch assigns the Cortex-A57 MIDR if AArch64 is enabled.
Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/ArmISA.py')
| -rw-r--r-- | src/arch/arm/ArmISA.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 3c1f7dd11..7b7189565 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -57,7 +57,11 @@ class ArmISA(SimObject): pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit") decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification") - midr = Param.UInt32(0x410fc0f0, "MIDR value") + # If no MIDR value is provided, 0x0 is treated by gem5 as follows: + # When 'highest_el_is_64' (AArch64 support) is: + # True -> Cortex-A57 TRM r0p0 MIDR is used + # False -> Cortex-A15 TRM r0p0 MIDR is used + midr = Param.UInt32(0x0, "MIDR value") # See section B4.1.89 - B4.1.92 of the ARM ARM # VMSAv7 support |