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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
| commit | 0d1ad50326a13a24daed916a069fc9f45775f51d (patch) | |
| tree | 69402307a753e23fb617538b93ad485f8e5b9598 /src/arch/arm/ArmSystem.py | |
| parent | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (diff) | |
| download | gem5-0d1ad50326a13a24daed916a069fc9f45775f51d.tar.xz | |
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable
as ISA parameter values. Additionally, setMiscReg now ignores writes
to all of the ID registers.
Note: This moves the MIDR parameter from ArmSystem to ArmISA for
consistency.
Diffstat (limited to 'src/arch/arm/ArmSystem.py')
| -rw-r--r-- | src/arch/arm/ArmSystem.py | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index ce363865c..763b043dc 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -50,12 +50,6 @@ class ArmSystem(System): type = 'ArmSystem' cxx_header = "arch/arm/system.hh" load_addr_mask = 0xffffffff - # 0x35 Implementor is '5' from "M5" - # 0x0 Variant - # 0xf Architecture from CPUID scheme - # 0xc00 Primary part number ("c" or higher implies ARM v7) - # 0x0 Revision - midr_regval = Param.UInt32(0x350fc000, "MIDR value") multi_proc = Param.Bool(True, "Multiprocessor system?") boot_loader = Param.String("", "File that contains the boot loader code if any") gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface") |