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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/arch/arm/ArmTLB.py | |
parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/arch/arm/ArmTLB.py')
-rw-r--r-- | src/arch/arm/ArmTLB.py | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 21253edef..fa9faaddf 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -34,25 +34,21 @@ from m5.params import * class ArmTLB(SimObject): abstract = True type = 'ArmTLB' - cxx_namespace = 'ArmISA' - cxx_class = 'TLB' + cxx_class = 'ArmISA::TLB' size = Param.Int("TLB size") class ArmDTB(ArmTLB): type = 'ArmDTB' - cxx_namespace = 'ArmISA' - cxx_class = 'DTB' + cxx_class = 'ArmISA::DTB' size = 64 class ArmITB(ArmTLB): type = 'ArmITB' - cxx_namespace = 'ArmISA' - cxx_class = 'ITB' + cxx_class = 'ArmISA::ITB' size = 64 class ArmUTB(ArmTLB): type = 'ArmUTB' - cxx_namespace = 'ArmISA' - cxx_class = 'UTB' + cxx_class = 'ArmISA::UTB' size = 64 |