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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
| commit | 0c99d21ad748371e801508a8c3652e07e2e56f93 (patch) | |
| tree | a2a52170a8a88ce919cecb4309428999e5380cfd /src/arch/arm/ArmTLB.py | |
| parent | 29acf859ebde2cf219ae636f60d8a46db7a1bb94 (diff) | |
| download | gem5-0c99d21ad748371e801508a8c3652e07e2e56f93.tar.xz | |
ARM: Squash outstanding walks when instructions are squashed.
Diffstat (limited to 'src/arch/arm/ArmTLB.py')
| -rw-r--r-- | src/arch/arm/ArmTLB.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 9572d2091..0a931b7e5 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -47,6 +47,8 @@ class ArmTableWalker(MemObject): cxx_class = 'ArmISA::TableWalker' port = MasterPort("Port for TableWalker to do walk the translation with") sys = Param.System(Parent.any, "system object parameter") + num_squash_per_cycle = Param.Unsigned(2, + "Number of outstanding walks that can be squashed per cycle") class ArmTLB(SimObject): type = 'ArmTLB' |