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author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 00:15:50 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 00:15:50 -0700 |
commit | f338d60930e973d330d13715b8617c22b980dcca (patch) | |
tree | d0980316aa40ff6f15699b752a2087035a634c65 /src/arch/arm/SConscript | |
parent | 020e923ba7f027b7b3b18ccf8ac208c576d75b95 (diff) | |
download | gem5-f338d60930e973d330d13715b8617c22b980dcca.tar.xz |
SE/FS: Build the Interrupt objects in SE mode.
Diffstat (limited to 'src/arch/arm/SConscript')
-rw-r--r-- | src/arch/arm/SConscript | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index a907e52fb..3dee08fbe 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -54,6 +54,7 @@ if env['TARGET_ISA'] == 'arm': Source('insts/pred_inst.cc') Source('insts/static_inst.cc') Source('insts/vfp.cc') + Source('interrupts.cc') Source('isa.cc') Source('miscregs.cc') Source('predecoder.cc') @@ -62,6 +63,7 @@ if env['TARGET_ISA'] == 'arm': Source('utility.cc') Source('remote_gdb.cc') + SimObject('ArmInterrupts.py') SimObject('ArmNativeTrace.py') SimObject('ArmTLB.py') @@ -70,14 +72,12 @@ if env['TARGET_ISA'] == 'arm': DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") DebugFlag('Predecoder', "Instructions returned by the predecoder") if env['FULL_SYSTEM']: - Source('interrupts.cc') Source('stacktrace.cc') Source('system.cc') Source('vtophys.cc') Source('linux/system.cc') Source('table_walker.cc') - SimObject('ArmInterrupts.py') SimObject('ArmSystem.py') else: Source('process.cc') |