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| author | Korey Sewell <ksewell@umich.edu> | 2009-07-31 10:40:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-07-31 10:40:42 -0400 |
| commit | aa75b9a7a7489bf86c4e6d406ff612e596ddff96 (patch) | |
| tree | 58a6816583a21c19c181e32bff10bf74aa9ad15f /src/arch/arm/SConscript | |
| parent | 60063cc700912666fa8b7968d692d00a1e82cb67 (diff) | |
| parent | 3dd3de5feb31055a48acb39575da25a9cea2626d (diff) | |
| download | gem5-aa75b9a7a7489bf86c4e6d406ff612e596ddff96.tar.xz | |
merge mips fix and statetrace changes
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 519435489..55ecabdc3 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -39,11 +39,14 @@ if env['TARGET_ISA'] == 'arm': Source('insts/mem.cc') Source('insts/pred_inst.cc') Source('insts/static_inst.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('tlb.cc') Source('vtophys.cc') + SimObject('ArmNativeTrace.py') SimObject('ArmTLB.py') + TraceFlag('Arm') if env['FULL_SYSTEM']: |