diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | cb9936cfdefdebf2c0b950f93a62d504d356524d (patch) | |
| tree | 3280784b875ccd23475c3f08edc774b50ef1c97d /src/arch/arm/SConscript | |
| parent | f246be4cbc27b4173f6917b430a31b9a39cdb380 (diff) | |
| download | gem5-cb9936cfdefdebf2c0b950f93a62d504d356524d.tar.xz | |
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 73fcc730b..67997f4e0 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -65,12 +65,14 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmTLB.py') TraceFlag('Arm') + TraceFlag('TLBVerbose') TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi") TraceFlag('Predecoder', "Instructions returned by the predecoder") if env['FULL_SYSTEM']: Source('interrupts.cc') Source('stacktrace.cc') Source('system.cc') + Source('table_walker.cc') SimObject('ArmInterrupts.py') SimObject('ArmSystem.py') |