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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:39 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:39 -0400 |
| commit | 3697990c27243f0c454f2fab0f12ed06759c97b9 (patch) | |
| tree | c7fe75d2cf328c26bc31cfe405d91afc2c4aa757 /src/arch/arm/SConscript | |
| parent | 132ea6319ab9292bef7c0ea87f396ef9de2db0fe (diff) | |
| download | gem5-3697990c27243f0c454f2fab0f12ed06759c97b9.tar.xz | |
arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as
described in the ARMv8 reference manual. It supports most of the
features of the PMU, however the following features are known to be
missing:
* Event filtering (e.g., from different privilege levels).
* Access controls (the PMU currently ignores the execution level).
* The chain counter (event no. 0x1E) is unimplemented.
The PMU itself does not implement any events, it merely provides an
interface for the configuration scripts to hook up probes that drive
events. Configuration scripts should call addEventProbe() to configure
custom events or high-level methods to configure architected
events. The Python implementation of addEventProbe() automatically
delays event type registration until after instantiation.
In order to support CPU switching and some combined counters (e.g.,
memory references synthesized from loads and stores), the PMU allows
multiple probes per event type. When creating a system that switches
between CPU models that share the same PMU, PMU events for all of the
CPU models can be registered with the PMU.
Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 78c0b01e9..92c46304c 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -62,11 +62,13 @@ if env['TARGET_ISA'] == 'arm': Source('insts/fplib.cc') Source('interrupts.cc') Source('isa.cc') + Source('isa_device.cc') Source('linux/linux.cc') Source('linux/process.cc') Source('linux/system.cc') Source('miscregs.cc') Source('nativetrace.cc') + Source('pmu.cc') Source('process.cc') Source('remote_gdb.cc') Source('stacktrace.cc') @@ -83,10 +85,12 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmNativeTrace.py') SimObject('ArmSystem.py') SimObject('ArmTLB.py') + SimObject('ArmPMU.py') DebugFlag('Arm') DebugFlag('Decoder', "Instructions returned by the predecoder") DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") + DebugFlag('PMUVerbose', "Performance Monitor") DebugFlag('TLBVerbose') # Add files generated by the ISA description. |