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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-12-23 09:31:17 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2014-12-23 09:31:17 -0500
commit184fefbb3bbaf93bccd65e73d3d08c7decc16e8a (patch)
tree0e8eb2625b018079821cddbdf1930144c4b762b7 /src/arch/arm/SConscript
parentb33812ba430bba0ab5ff4e6372b47f4b323f0891 (diff)
downloadgem5-184fefbb3bbaf93bccd65e73d3d08c7decc16e8a.tar.xz
arm: Raise an alignment fault if a PC has illegal alignment
We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow.
Diffstat (limited to 'src/arch/arm/SConscript')
-rw-r--r--src/arch/arm/SConscript1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 92c46304c..a4740a9bc 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/misc.cc')
Source('insts/misc64.cc')
Source('insts/pred_inst.cc')
+ Source('insts/pseudo.cc')
Source('insts/static_inst.cc')
Source('insts/vfp.cc')
Source('insts/fplib.cc')