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authorGabe Black <gblack@eecs.umich.edu>2011-11-02 01:25:15 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-11-02 01:25:15 -0700
commit239b33e016b19aa18e70f3bc64c4e11de3f92c7d (patch)
tree87008a6ac9437f57bb9a33b240603fe090b4b0ab /src/arch/arm/SConscript
parent7b417d4188c4978ecdeddd04a0b53f60b96d22e1 (diff)
downloadgem5-239b33e016b19aa18e70f3bc64c4e11de3f92c7d.tar.xz
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
Diffstat (limited to 'src/arch/arm/SConscript')
-rw-r--r--src/arch/arm/SConscript15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index daa083a22..171c04718 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -56,11 +56,16 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/vfp.cc')
Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('miscregs.cc')
Source('nativetrace.cc')
Source('predecoder.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
+ Source('system.cc')
Source('table_walker.cc')
Source('tlb.cc')
Source('utility.cc')
@@ -68,21 +73,13 @@ if env['TARGET_ISA'] == 'arm':
SimObject('ArmInterrupts.py')
SimObject('ArmNativeTrace.py')
+ SimObject('ArmSystem.py')
SimObject('ArmTLB.py')
DebugFlag('Arm')
DebugFlag('TLBVerbose')
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('Predecoder', "Instructions returned by the predecoder")
- if env['FULL_SYSTEM']:
- Source('system.cc')
- Source('linux/system.cc')
-
- SimObject('ArmSystem.py')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')