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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
commit997f36c7115e37f292c50db8986c6ebd4bd1beca (patch)
tree066f9abaa93c3dd1509d6f1b25acb731c64e87fa /src/arch/arm/SConscript
parentaa031e1c116bc8bf22c844b4a9f3d2b3c69f995a (diff)
downloadgem5-997f36c7115e37f292c50db8986c6ebd4bd1beca.tar.xz
Registers: Collapse ARM and MIPS regfile directories.
--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
Diffstat (limited to 'src/arch/arm/SConscript')
-rw-r--r--src/arch/arm/SConscript2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index a88a911f7..ea55314a4 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -41,7 +41,7 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/static_inst.cc')
Source('isa.cc')
Source('pagetable.cc')
- Source('regfile/regfile.cc')
+ Source('regfile.cc')
Source('tlb.cc')
Source('vtophys.cc')