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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-27 17:31:46 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-06 09:58:41 +0000 |
| commit | d251fab8514f7a209044b69688aa3615f112e57d (patch) | |
| tree | 9c4b74297832bb048e3825189f1930c5b1126e7a /src/arch/arm/SConscript | |
| parent | 96bba0c50cda359b23365e3cb3a3f295796b06e4 (diff) | |
| download | gem5-d251fab8514f7a209044b69688aa3615f112e57d.tar.xz | |
arch-arm: Fix AArch32 branch instructions disassemble
This patch adds the generateDisassembly method for BranchReg, BranchImm
and BranchRegReg Base classes used by AArch32 branch instructions.
Change-Id: I6de015cc213335556d5187df3d4fcd765876262c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/SConscript')
| -rw-r--r-- | src/arch/arm/SConscript | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 6ef445e10..d9b5661ca 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -49,6 +49,7 @@ if env['TARGET_ISA'] == 'arm': Dir('isa/formats') Source('decoder.cc') Source('faults.cc') + Source('insts/branch.cc') Source('insts/branch64.cc') Source('insts/data64.cc') Source('insts/macromem.cc') |