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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-31 09:41:48 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-18 13:30:01 +0000 |
commit | a4bf7c3c20756f01f39e644d65f97fd9813502f0 (patch) | |
tree | f9488099d2ccdddce14473881d82d59be82b0605 /src/arch/arm/ccregs.hh | |
parent | dc70987e470d66f584e0ddf606e9f07da994ba75 (diff) | |
download | gem5-a4bf7c3c20756f01f39e644d65f97fd9813502f0.tar.xz |
arch-arm: Fix Data Abort ISS when caused by Atomic operation
Data Aborts caused by an atomic instruction have a special rule for
their syndrome:
From a ISS point of view they count as read if a read to that address
would generate a fault; they count as writes otherwise (ISS.WnR bit)
This patch is implementing this in the TLB. For permission faults we
need to explicitly check if a read would trigger a fault
(e.g. checking for the AP bits) since permissions can allow read-only
accesses.
For other MMU exceptions (like translation faults) we are confident the
nature of the access doesn't affect the genration of a fault.
This means that if the access is atomic, we treat it as a read from an
ISS.WnR point of view.
Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/ccregs.hh')
0 files changed, 0 insertions, 0 deletions