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authorGabe Black <gblack@eecs.umich.edu>2012-05-25 00:55:24 -0700
committerGabe Black <gblack@eecs.umich.edu>2012-05-25 00:55:24 -0700
commiteae1e97fb002b44a9d8c46df2da1ddc1d0156ce4 (patch)
tree56805ea5d0817aff8febe4bea280f4cb5e5f8acf /src/arch/arm/decoder.hh
parent276f3e9535e72c8e9764b5f7369e1fa9eb055055 (diff)
downloadgem5-eae1e97fb002b44a9d8c46df2da1ddc1d0156ce4.tar.xz
ISA: Make the decode function part of the ISA's decoder.
Diffstat (limited to 'src/arch/arm/decoder.hh')
-rw-r--r--src/arch/arm/decoder.hh24
1 files changed, 21 insertions, 3 deletions
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 5525b4a89..a91d70f48 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -31,13 +31,31 @@
#ifndef __ARCH_ARM_DECODER_HH__
#define __ARCH_ARM_DECODER_HH__
-#include "arch/generic/decoder.hh"
+#include "arch/types.hh"
+#include "cpu/decode_cache.hh"
+#include "cpu/static_inst_fwd.hh"
namespace ArmISA
{
-class Decoder : public GenericISA::Decoder
-{};
+class Decoder
+{
+ protected:
+ /// A cache of decoded instruction objects.
+ static DecodeCache defaultCache;
+
+ public:
+ StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+ /// Decode a machine instruction.
+ /// @param mach_inst The binary instruction to decode.
+ /// @retval A pointer to the corresponding StaticInst object.
+ StaticInstPtr
+ decode(ExtMachInst mach_inst, Addr addr)
+ {
+ return defaultCache.decode(this, mach_inst, addr);
+ }
+};
} // namespace ArmISA