fastmodel: Add glue code which adapts fastmodels to run in gem5.

Fast Models are models written by ARM which emulate different
components of a computer system. They can be combined into small
subsystems and then exported as systemc modules.

To enable this code, you'll need to set USE_ARM_FASTMODEL variable to
true. This CL does not include the fast models themselves, or a license
to use them or the associated tools. To build these fast models, you'll
need to set some scons variables. These variables should be set as
described in the fast model distribution.

* PVLIB_HOME
* MAXCORE_HOME
* ARMLMD_LICENSE_FILE

Some minor patches to source filesdistributed with the fast model code
may be necessary since their use of systemc is not necessarily 100%
standards compliant.

Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 110 insertions, 0 deletions

diff --git a/src/arch/arm/fastmodel/FastModel.py b/src/arch/arm/fastmodel/FastModel.py
new file mode 100644
index 000000000..ccc5e2c49
--- /dev/null
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -0,0 +1,110 @@
+# Copyright 2019 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+
+from m5.objects.SystemC import SystemC_ScModule
+from m5.objects.Tlm import TlmInitiatorSocket, TlmTargetSocket
+
+def AMBA_TARGET_ROLE(width):
+    return 'AMBA TARGET %d' % width
+
+def AMBA_INITIATOR_ROLE(width):
+    return 'AMBA INITIATOR %d' % width
+
+def SC_MASTER_PORT_ROLE(port_type):
+    return 'SC MASTER PORT for %s' % port_type
+
+def SC_SLAVE_PORT_ROLE(port_type):
+    return 'SC SLAVE PORT for %s' % port_type
+
+class AmbaTargetSocket(Port):
+    def __init__(self, width, desc):
+        my_role = AMBA_INITIATOR_ROLE(width)
+        peer_role = AMBA_TARGET_ROLE(width)
+        Port.compat(my_role, peer_role)
+
+        super(AmbaTargetSocket, self).__init__(my_role, desc)
+
+class VectorAmbaTargetSocket(VectorPort):
+    def __init__(self, width, desc):
+        my_role = AMBA_INITIATOR_ROLE(width)
+        peer_role = AMBA_TARGET_ROLE(width)
+        Port.compat(my_role, peer_role)
+
+        super(VectorAmbaTargetSocket, self).__init__(my_role, desc)
+
+class AmbaInitiatorSocket(Port):
+    def __init__(self, width, desc):
+        my_role = AMBA_TARGET_ROLE(width)
+        peer_role = AMBA_INITIATOR_ROLE(width)
+        Port.compat(my_role, peer_role)
+
+        super(AmbaInitiatorSocket, self).__init__(
+                my_role, desc, is_source=True)
+
+class VectorAmbaInitiatorSocket(VectorPort):
+    def __init__(self, width, desc):
+        my_role = AMBA_TARGET_ROLE(width)
+        peer_role = AMBA_INITIATOR_ROLE(width)
+        Port.compat(my_role, peer_role)
+
+        super(VectorAmbaInitiatorSocket, self).__init__(
+                my_role, desc, is_source=True)
+
+class ScMasterPort(Port):
+    def __init__(self, desc, port_type):
+        my_role = SC_MASTER_PORT_ROLE(port_type)
+        peer_role = SC_SLAVE_PORT_ROLE(port_type)
+        Port.compat(my_role, peer_role)
+
+        super(ScMasterPort, self).__init__(my_role, desc)
+
+class ScSlavePort(Port):
+    def __init__(self, desc, port_type):
+        my_role = SC_SLAVE_PORT_ROLE(port_type)
+        peer_role = SC_MASTER_PORT_ROLE(port_type)
+        Port.compat(my_role, peer_role)
+
+        super(ScSlavePort, self).__init__(my_role, desc)
+
+class AmbaToTlmBridge64(SystemC_ScModule):
+    type = 'AmbaToTlmBridge64'
+    cxx_class = 'FastModel::AmbaToTlmBridge64'
+    cxx_header = 'arch/arm/fastmodel/amba_to_tlm_bridge.hh'
+
+    amba = AmbaTargetSocket(64, 'AMBA PV target socket')
+    tlm = TlmInitiatorSocket(64, 'TLM initiator socket')
+
+class AmbaFromTlmBridge64(SystemC_ScModule):
+    type = 'AmbaFromTlmBridge64'
+    cxx_class = 'FastModel::AmbaFromTlmBridge64'
+    cxx_header = 'arch/arm/fastmodel/amba_from_tlm_bridge.hh'
+
+    tlm = TlmTargetSocket(64, 'TLM target socket')
+    amba = AmbaInitiatorSocket(64, 'AMBA PV initiator socket')