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| author | Gabe Black <gabeblack@google.com> | 2019-10-18 17:49:45 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-12-17 23:17:28 +0000 |
| commit | 1b48cfd7617e3cd54086121d36ad8364a29f1d90 (patch) | |
| tree | 14a28100cc52dcc58bee74811d8c1f2effa66ef1 /src/arch/arm/fastmodel/iris/cpu.cc | |
| parent | 973842282f74fe801f406e6c8fc2ef03d0aecdba (diff) | |
| download | gem5-1b48cfd7617e3cd54086121d36ad8364a29f1d90.tar.xz | |
fastmodel: Implement port proxies.
This plumbing is simple and largely copied from other implementations
within gem5. This mechanism should be refactored so that the
duplication is unnecessary.
Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/fastmodel/iris/cpu.cc')
| -rw-r--r-- | src/arch/arm/fastmodel/iris/cpu.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc index 8284d1717..d66cf1dbc 100644 --- a/src/arch/arm/fastmodel/iris/cpu.cc +++ b/src/arch/arm/fastmodel/iris/cpu.cc @@ -78,4 +78,12 @@ BaseCPU::totalInsts() const return count; } +void +BaseCPU::init() +{ + ::BaseCPU::init(); + for (auto *tc: threadContexts) + tc->initMemProxies(tc); +} + } // namespace Iris |