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| author | Gabe Black <gabeblack@google.com> | 2019-11-11 16:30:27 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2020-01-22 07:11:58 +0000 |
| commit | 1db6e702e9f016e4c44a784d78c6894b8d224454 (patch) | |
| tree | 21aa0268b768670622d2a9f3a522979761e46aaf /src/arch/arm/fastmodel/iris | |
| parent | 4252c03c3f4ee7aed09a1bccfbd5855052cbbc03 (diff) | |
| download | gem5-1db6e702e9f016e4c44a784d78c6894b8d224454.tar.xz | |
fastmodel: Implement CC reg accessors.
Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/fastmodel/iris')
| -rw-r--r-- | src/arch/arm/fastmodel/iris/thread_context.cc | 19 | ||||
| -rw-r--r-- | src/arch/arm/fastmodel/iris/thread_context.hh | 17 |
2 files changed, 24 insertions, 12 deletions
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index b9d34e4bd..c18a5cd7d 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -520,6 +520,25 @@ ThreadContext::setIntReg(RegIndex reg_idx, RegVal val) call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val); } +RegVal +ThreadContext::readCCRegFlat(RegIndex idx) const +{ + if (idx >= ccRegIds.size()) + return 0; + iris::ResourceReadResult result; + call().resource_read(_instId, result, ccRegIds.at(idx)); + return result.data.at(0); +} + +void +ThreadContext::setCCRegFlat(RegIndex idx, RegVal val) +{ + panic_if(idx >= ccRegIds.size(), + "CC reg %d is not supported by fast model.", idx); + iris::ResourceWriteResult result; + call().resource_write(_instId, result, ccRegIds.at(idx), val); +} + const ArmISA::VecRegContainer & ThreadContext::readVecReg(const RegId ®_id) const { diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index 77f3ec9fa..5d6827cc9 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -83,6 +83,7 @@ class ThreadContext : public ::ThreadContext ResourceIds miscRegIds; ResourceIds intReg32Ids; ResourceIds intReg64Ids; + ResourceIds ccRegIds; iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX; iris::ResourceId icountRscId; @@ -386,7 +387,7 @@ class ThreadContext : public ::ThreadContext RegVal readCCReg(RegIndex reg_idx) const override { - panic("%s not implemented.", __FUNCTION__); + return readCCRegFlat(reg_idx); } void setIntReg(RegIndex reg_idx, RegVal val) override; @@ -419,7 +420,7 @@ class ThreadContext : public ::ThreadContext void setCCReg(RegIndex reg_idx, RegVal val) override { - panic("%s not implemented.", __FUNCTION__); + setCCRegFlat(reg_idx, val); } void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); } @@ -547,16 +548,8 @@ class ThreadContext : public ::ThreadContext panic("%s not implemented.", __FUNCTION__); } - RegVal - readCCRegFlat(RegIndex idx) const override - { - panic("%s not implemented.", __FUNCTION__); - } - void - setCCRegFlat(RegIndex idx, RegVal val) override - { - panic("%s not implemented.", __FUNCTION__); - } + RegVal readCCRegFlat(RegIndex idx) const override; + void setCCRegFlat(RegIndex idx, RegVal val) override; /** @} */ }; |