fastmodel: Refactor the CortexA76x1 model for MP support.

This change inverts the relationship between the fast model and gem5
CPUs, and factors out the parts of the CortexA76x1 which are per core
vs. per cluster.

Change-Id: I33eacc2461f08c7fd1784936b230e96c768c0e79
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21501
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

3 files changed, 5 insertions, 14 deletions

diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py
index 781a146ad..b6dbf8726 100644
--- a/src/arch/arm/fastmodel/iris/Iris.py
+++ b/src/arch/arm/fastmodel/iris/Iris.py
@@ -49,7 +49,7 @@ class IrisBaseCPU(BaseCPU):
         #TODO Make this work.
         return False
 
-    evs = Param.SystemC_ScModule(Parent.any,
+    evs = Param.SystemC_ScModule(
             "Fast model exported virtual subsystem holding cores")
-    core_paths = VectorParam.String(
-            "Sub-paths to elements in the EVS which are cores")
+    thread_paths = VectorParam.String(
+            "Sub-paths to elements in the EVS which support a thread context")
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index 63cd731dc..8284d1717 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -40,15 +40,6 @@ BaseCPU::BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs) :
 {
     sc_core::sc_attr_base *base;
 
-    base = evs->get_attribute(Gem5CpuAttributeName);
-    auto *gem5_cpu_attr =
-        dynamic_cast<sc_core::sc_attribute<::BaseCPU *> *>(base);
-    panic_if(base && !gem5_cpu_attr,
-             "The EVS gem5 CPU attribute was not of type "
-             "sc_attribute<::BaesCPU *>.");
-    if (gem5_cpu_attr)
-        gem5_cpu_attr->value = this;
-
     const auto &event_vec = evs->get_child_events();
     auto event_it = std::find_if(event_vec.begin(), event_vec.end(),
             [](const sc_core::sc_event *e) -> bool {
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index f7be5cb76..911743b74 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -48,7 +48,7 @@ static const std::string ClockEventName = "gem5_clock_period_event";
 static const std::string PeriodAttributeName = "gem5_clock_period_attribute";
 // The name of the attribute the subsystem should create which will be set to
 // a pointer to its corresponding gem5 CPU.
-static const std::string Gem5CpuAttributeName = "gem5_cpu";
+static const std::string Gem5CpuClusterAttributeName = "gem5_cpu_cluster";
 // The name of the attribute the subsystem should create to hold the
 // sendFunctional delegate for port proxies.
 static const std::string SendFunctionalAttributeName = "gem5_send_functional";
@@ -133,7 +133,7 @@ class CPU : public Iris::BaseCPU
         System *sys = params->system;
 
         int thread_id = 0;
-        for (const std::string &sub_path: params->core_paths) {
+        for (const std::string &sub_path: params->thread_paths) {
             std::string path = parent_path + "." + sub_path;
             auto *tc = new TC(this, thread_id++, sys, iris_if, path);
             threadContexts.push_back(tc);