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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-20 13:33:34 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-03-08 10:10:39 +0000
commit689221c651035ebb8be411893a9cc73f17bba9fb (patch)
tree544fab26e32c15f84ec15bfae2e07c5ca252c5bd /src/arch/arm/faults.cc
parent208b1fc47e53206061751c9915ae9e129f9e89e5 (diff)
downloadgem5-689221c651035ebb8be411893a9cc73f17bba9fb.tar.xz
arch-arm: Fix PCAlignmentFault routing to Hypervisor
This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions. Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
-rw-r--r--src/arch/arm/faults.cc14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index c36848ecf..1d6d01592 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1432,6 +1432,20 @@ PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
tc->setMiscReg(getFaultAddrReg64(), faultPC);
}
+bool
+PCAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+ bool toHyp = false;
+
+ SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+ HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+ // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+ toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+ return toHyp;
+}
+
SPAlignmentFault::SPAlignmentFault()
{}