diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:50 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:50 -0600 |
| commit | 2eb19dac6506efa16cd39c2b64c85163f48ab1c1 (patch) | |
| tree | 2b816d9c55f2159b29b6d2737f943eba86f7de20 /src/arch/arm/faults.cc | |
| parent | 916c7f162da6fe638cd6a78d40ac64a83cf54e5f (diff) | |
| download | gem5-2eb19dac6506efa16cd39c2b64c85163f48ab1c1.tar.xz | |
ARM: Set ITSTATE correctly after FlushPipe
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index e388c72a8..9ce2e2da4 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -220,6 +220,7 @@ FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) { // start refetching from the next instruction. PCState pc = tc->pcState(); assert(inst); + pc.forcedItState(inst->machInst.newItstate); inst->advancePC(pc); tc->pcState(pc); } |