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| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2011-05-23 10:40:18 -0500 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2011-05-23 10:40:18 -0500 |
| commit | 6dd996aabbfcd6c519e70ded3b54e44159deb685 (patch) | |
| tree | 81972e7c2829a2170c792558ecce47d7a55881cf /src/arch/arm/faults.cc | |
| parent | fc1d2d967924f9e8116d156550786ed0b527d1e3 (diff) | |
| download | gem5-6dd996aabbfcd6c519e70ded3b54e44159deb685.tar.xz | |
O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.
A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 7dd81a681..3bd9f070c 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -219,6 +219,8 @@ AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst) fsr.ext = 0; tc->setMiscReg(T::FsrIndex, fsr); tc->setMiscReg(T::FarIndex, faultAddr); + + DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr); } void |