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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-06-23 14:49:56 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-22 16:12:38 +0000 |
commit | e80899c49a758d966ae47920c296325d64fea383 (patch) | |
tree | 5521bb4501cf4ebc7b3a60f05c8db466a70f81b9 /src/arch/arm/faults.cc | |
parent | eac97c91da74acb602c580b36415ab4c6b08b582 (diff) | |
download | gem5-e80899c49a758d966ae47920c296325d64fea383.tar.xz |
arch-arm: Add support for the brk instruction
Add support for software breakpoints as signalled by the aarch64 brk
instruction. This introduces a new SoftwareBreakpoint fault.
Change-Id: I93646c3298e09d7f7b0983108ba8937c7331297a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5721
Reviewed-by: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
-rw-r--r-- | src/arch/arm/faults.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index ef9d05a13..0293ee100 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -278,6 +278,11 @@ template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() }; +template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = { + // Some dummy values (SoftwareBreakpoint is AArch64-only) + "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, + 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT, FaultStat() +}; template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { // Some dummy values "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, @@ -1393,6 +1398,25 @@ SystemError::routeToHyp(ThreadContext *tc) const return toHyp; } + +SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) + : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) +{} + +bool +SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const +{ + assert(from64); + + const bool have_el2 = ArmSystem::haveVirtualization(tc); + + const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); + const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); + + return have_el2 && !inSecureState(tc) && fromEL <= EL1 && + (hcr.tge || mdcr.tde); +} + void ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { DPRINTF(Faults, "Invoking ArmSev Fault\n"); @@ -1425,6 +1449,7 @@ template class ArmFaultVals<SecureMonitorTrap>; template class ArmFaultVals<PCAlignmentFault>; template class ArmFaultVals<SPAlignmentFault>; template class ArmFaultVals<SystemError>; +template class ArmFaultVals<SoftwareBreakpoint>; template class ArmFaultVals<ArmSev>; template class AbortFault<PrefetchAbort>; template class AbortFault<DataAbort>; |