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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-31 14:57:30 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-11-07 15:22:43 +0000 |
| commit | 46a79f7d10f7b8eabd4e3bb45ff50959d04a2571 (patch) | |
| tree | 1b1f4a4216a542ea96388e9ceab5fe2fbbe5efdc /src/arch/arm/faults.cc | |
| parent | 4e02b9219d18fba0923b6624b12cf283bd238216 (diff) | |
| download | gem5-46a79f7d10f7b8eabd4e3bb45ff50959d04a2571.tar.xz | |
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
The patch is also moving some initialization code to be used
by AArch64 as well since the registers are mapped to AArch64 ones.
Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13997
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
0 files changed, 0 insertions, 0 deletions