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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:21 -0700
commit5c37d10624e0f9a9568f1eb1527832c55addba59 (patch)
tree7283390137489bc23fd4685e6ede83925479ee48 /src/arch/arm/faults.cc
parent9bf22992ee1f5088ae5e513acaa7aabee048c4bd (diff)
downloadgem5-5c37d10624e0f9a9568f1eb1527832c55addba59.tar.xz
Registers: Eliminate the ISA defined RegFile class.
Diffstat (limited to 'src/arch/arm/faults.cc')
-rw-r--r--src/arch/arm/faults.cc2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index b79c09174..3d882c97f 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -433,7 +433,6 @@ void InterruptFault::invoke(ThreadContext *tc)
{
#if FULL_SYSTEM
DPRINTF(Arm,"%s encountered.\n", name());
- //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
@@ -469,7 +468,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc)
{
#if FULL_SYSTEM
DPRINTF(Arm,"%s encountered.\n", name());
- //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector