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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-05 16:17:48 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-22 10:53:40 +0000 |
| commit | b4a10d55e55752c3423a9d0f4b529f7f80432590 (patch) | |
| tree | 34f6f36084709e9e2ea1568e3a5ff9051d9c5d57 /src/arch/arm/faults.cc | |
| parent | fc278fffb78512ff3d62a906804d6b285edd00c7 (diff) | |
| download | gem5-b4a10d55e55752c3423a9d0f4b529f7f80432590.tar.xz | |
arch-arm: AArch32 execution triggering AArch64 SW Break
AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when
interprocessing if the trapping conditions are met.
Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11197
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index cf58960ec..ab0d0de0f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1533,8 +1533,6 @@ SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) bool SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const { - assert(from64); - const bool have_el2 = ArmSystem::haveVirtualization(tc); const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); |