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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 16:30:33 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-14 13:45:49 +0000 |
| commit | fe8faa62b74087febe227f69385db3e562682799 (patch) | |
| tree | 2ae38f63d387a49c048f3dc9f71f07eb70bce1ce /src/arch/arm/faults.cc | |
| parent | 831184d2949fbd790a2040738079ca03c8cfdefe (diff) | |
| download | gem5-fe8faa62b74087febe227f69385db3e562682799.tar.xz | |
arch-arm: Add Illegal Execution flag to PCState
This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage. This is
done by adding the illegalExecution field to the PCState.
Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 676559f61..dd4f9581c 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -601,6 +601,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) pc.nextJazelle(pc.jazelle()); pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); + pc.illegalExec(false); tc->pcState(pc); } @@ -684,6 +685,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) PCState pc(new_pc); pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); + pc.illegalExec(false); tc->pcState(pc); // If we have a valid instruction then use it to annotate this fault with |