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author | Gabor Dozsa <gabor.dozsa@arm.com> | 2019-06-11 11:47:26 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-18 15:09:22 +0000 |
commit | 9130f5427d7009c4f40e0097b79b4972430a27c3 (patch) | |
tree | 98f39295d24a16637c2fba641ef66b4a0741663a /src/arch/arm/faults.cc | |
parent | ddd3f43f8a590cd287cd3449ea6e49bc48dad06a (diff) | |
download | gem5-9130f5427d7009c4f40e0097b79b4972430a27c3.tar.xz |
arch-arm: Add first-/non-faulting load instructions
First-/non-faulting loads are part of Arm SVE.
Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
-rw-r--r-- | src/arch/arm/faults.cc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 94374714b..a03c91703 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1216,6 +1216,14 @@ AbortFault<T>::isMMUFault() const (source < ArmFault::PermissionLL + 4)); } +template<class T> +bool +AbortFault<T>::getFaultVAddr(Addr &va) const +{ + va = (stage2 ? OVAddr : faultAddr); + return true; +} + ExceptionClass PrefetchAbort::ec(ThreadContext *tc) const { @@ -1618,5 +1626,29 @@ template class AbortFault<VirtualDataAbort>; IllegalInstSetStateFault::IllegalInstSetStateFault() {} +bool +getFaultVAddr(Fault fault, Addr &va) +{ + auto arm_fault = dynamic_cast<ArmFault *>(fault.get()); + + if (arm_fault) { + return arm_fault->getFaultVAddr(va); + } else { + auto pgt_fault = dynamic_cast<GenericPageTableFault *>(fault.get()); + if (pgt_fault) { + va = pgt_fault->getFaultVAddr(); + return true; + } + + auto align_fault = dynamic_cast<GenericAlignmentFault *>(fault.get()); + if (align_fault) { + va = align_fault->getFaultVAddr(); + return true; + } + + // Return false since it's not an address triggered exception + return false; + } +} } // namespace ArmISA |