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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-15 13:30:46 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 14:23:19 +0000 |
| commit | e97a1fe390a91f30042d683ebc5e654d39844eda (patch) | |
| tree | cb65b1a95de5bec2642af955ad54205f159f9db0 /src/arch/arm/faults.cc | |
| parent | 4ccb1ea710dcdcf179726448596b96c8e44f743a (diff) | |
| download | gem5-e97a1fe390a91f30042d683ebc5e654d39844eda.tar.xz | |
arch-arm: Replace direct use cpsr.el with currEL helper
The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.
Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/faults.cc')
| -rw-r--r-- | src/arch/arm/faults.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 0f279fab4..ba5151944 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1014,7 +1014,7 @@ SupervisorTrap::routeToHyp(ThreadContext *tc) const CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector - toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); + toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0); return toHyp; } @@ -1536,7 +1536,7 @@ PCAlignmentFault::routeToHyp(ThreadContext *tc) const CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector - toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); + toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0); return toHyp; } |