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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit23626d99af9469b5a86f510e0542846f5af65cbd (patch)
treecac4ec64670fe842af14a0183ae7d53b44ba9478 /src/arch/arm/faults.hh
parent1fd104fc35ed5a1fa01e5709aba0dec58a5db6f5 (diff)
downloadgem5-23626d99af9469b5a86f510e0542846f5af65cbd.tar.xz
ARM: Make sure that software prefetch instructions can't change the state of the TLB
Diffstat (limited to 'src/arch/arm/faults.hh')
-rw-r--r--src/arch/arm/faults.hh6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index d8684792c..f9d25abdf 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -87,6 +87,12 @@ class ArmFault : public FaultBase
MemoryAccessSynchronousParityError = 0x19,
TranslationTableWalkPrtyErr0 = 0x1c,
TranslationTableWalkPrtyErr1 = 0x1e,
+
+ // not a real fault. This is a status code
+ // to allow the translation function to inform
+ // the memory access function not to proceed
+ // for a Prefetch that misses in the TLB.
+ PrefetchTLBMiss
};
struct FaultVals