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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
commit | 481eb6ae8018d0478c23fda7c5f9f3fa4db8de89 (patch) | |
tree | e9b449bc6a2e7b15255c7a3c2d5984e0a99b452c /src/arch/arm/faults.hh | |
parent | 9ffe0e7ba67ee194db885b96a7ed3630aed03584 (diff) | |
download | gem5-481eb6ae8018d0478c23fda7c5f9f3fa4db8de89.tar.xz |
arm: Fixes based on UBSan and static analysis
Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.
Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
Diffstat (limited to 'src/arch/arm/faults.hh')
-rw-r--r-- | src/arch/arm/faults.hh | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 4980c12e1..ef87ee145 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -172,7 +172,8 @@ class ArmFault : public FaultBase }; ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : - machInst(_machInst), issRaw(_iss), from64(false), to64(false) {} + machInst(_machInst), issRaw(_iss), from64(false), to64(false), + fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {} // Returns the actual syndrome register to use based on the target // exception level @@ -395,9 +396,11 @@ class AbortFault : public ArmFaultVals<T> ArmFault::TranMethod tranMethod; public: - AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, - bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : - faultAddr(_faultAddr), write(_write), domain(_domain), source(_source), + AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, + uint8_t _source, bool _stage2, + ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : + faultAddr(_faultAddr), OVAddr(0), write(_write), + domain(_domain), source(_source), srcEncoded(0), stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) {} |