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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-12-01 13:24:29 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-12-21 13:25:24 +0000 |
| commit | 0049df179f3b5f57218b91e98390c1aacaa27c2e (patch) | |
| tree | 4830ffae7fe4f758e58ef7ad06a1f8d8853d2efb /src/arch/arm/faults.hh | |
| parent | f9d6cf7eff123724a31e95195abcabc560481dda (diff) | |
| download | gem5-0049df179f3b5f57218b91e98390c1aacaa27c2e.tar.xz | |
arch-arm: Hyp routed undef fault need to change its syndrome
If undefined instruction has to be routed to EL2, the HSR register
must change the HSR.EC and HSR.ISS accordingly, which means not using
the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)
Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6621
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.hh')
| -rw-r--r-- | src/arch/arm/faults.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 3191ceb88..fa6740a1a 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -73,6 +73,8 @@ class ArmFault : public FaultBase ExceptionLevel toEL; // Target exception level OperatingMode fromMode; // Source operating mode + bool hypRouted; // True if the fault has been routed to Hypervisor + Addr getVector(ThreadContext *tc); Addr getVector64(ThreadContext *tc); @@ -173,7 +175,7 @@ class ArmFault : public FaultBase ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : machInst(_machInst), issRaw(_iss), from64(false), to64(false), - fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {} + fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false) {} // Returns the actual syndrome register to use based on the target // exception level |