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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:33:34 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-08 10:10:39 +0000 |
| commit | 689221c651035ebb8be411893a9cc73f17bba9fb (patch) | |
| tree | 544fab26e32c15f84ec15bfae2e07c5ca252c5bd /src/arch/arm/faults.hh | |
| parent | 208b1fc47e53206061751c9915ae9e129f9e89e5 (diff) | |
| download | gem5-689221c651035ebb8be411893a9cc73f17bba9fb.tar.xz | |
arch-arm: Fix PCAlignmentFault routing to Hypervisor
This patch enables PCAlignmentFault routing to Hypervisor in case
HCR_EL2.TGE == 1, as is happening for other arm exceptions.
Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8841
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/faults.hh')
| -rw-r--r-- | src/arch/arm/faults.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index d99116fb9..537405cf2 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -535,6 +535,7 @@ class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> {} void invoke(ThreadContext *tc, const StaticInstPtr &inst = StaticInst::nullStaticInstPtr) override; + bool routeToHyp(ThreadContext *tc) const override; }; /// Stack pointer alignment fault (AArch64 only) |