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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch) | |
| tree | 273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/faults.hh | |
| parent | 3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff) | |
| download | gem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz | |
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/faults.hh')
| -rw-r--r-- | src/arch/arm/faults.hh | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 7339e0e63..7e4013a85 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -128,8 +128,15 @@ class ArmFaultVals : public ArmFault bool fiqDisable() { return vals.fiqDisable; } }; - -class Reset : public ArmFaultVals<Reset> {}; +class Reset : public ArmFaultVals<Reset> +#if FULL_SYSTEM +{ + public: + void invoke(ThreadContext *tc); +}; +#else +{}; +#endif //FULL_SYSTEM class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> { |