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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-29 12:38:12 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-05 15:50:57 +0000 |
| commit | 361bc8b47260a55902764054d3ac25694ac93f8a (patch) | |
| tree | e6929b787500aa227333b4fe90fc4047838ef8c0 /src/arch/arm/faults.hh | |
| parent | fd1a8bed393a2ef48d584fcabeee4d98eda0e3fa (diff) | |
| download | gem5-361bc8b47260a55902764054d3ac25694ac93f8a.tar.xz | |
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state
bit is 1, any privileged data access from EL1 or EL2 to a virtual memory
address that is accessible at EL0 generates a Permission fault.
This feature is mandatory in ARMv8.1 implementations.
This feature is supported in AArch64 and AArch32 states.
The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields
identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I94a76311711739dd2394c72944d88ba9321fd159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/faults.hh')
| -rw-r--r-- | src/arch/arm/faults.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index d14983d28..5e68875f5 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited + * Copyright (c) 2010, 2012-2013, 2016-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -82,6 +82,7 @@ class ArmFault : public FaultBase bool faultUpdated; bool hypRouted; // True if the fault has been routed to Hypervisor + bool span; // True if the fault is setting the PSTATE.PAN bit virtual Addr getVector(ThreadContext *tc); Addr getVector64(ThreadContext *tc); @@ -200,7 +201,7 @@ class ArmFault : public FaultBase ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : machInst(_machInst), issRaw(_iss), from64(false), to64(false), fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), - faultUpdated(false), hypRouted(false) {} + faultUpdated(false), hypRouted(false), span(false) {} // Returns the actual syndrome register to use based on the target // exception level |