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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-27 17:31:46 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-06 09:58:41 +0000 |
| commit | d251fab8514f7a209044b69688aa3615f112e57d (patch) | |
| tree | 9c4b74297832bb048e3825189f1930c5b1126e7a /src/arch/arm/insts/branch.hh | |
| parent | 96bba0c50cda359b23365e3cb3a3f295796b06e4 (diff) | |
| download | gem5-d251fab8514f7a209044b69688aa3615f112e57d.tar.xz | |
arch-arm: Fix AArch32 branch instructions disassemble
This patch adds the generateDisassembly method for BranchReg, BranchImm
and BranchRegReg Base classes used by AArch32 branch instructions.
Change-Id: I6de015cc213335556d5187df3d4fcd765876262c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/insts/branch.hh')
| -rw-r--r-- | src/arch/arm/insts/branch.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh index cc320dbff..9bc8cb8f7 100644 --- a/src/arch/arm/insts/branch.hh +++ b/src/arch/arm/insts/branch.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010,2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -58,6 +58,7 @@ class BranchImm : public PredOp PredOp(mnem, _machInst, __opClass), imm(_imm) {} + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with an immediate @@ -85,6 +86,8 @@ class BranchReg : public PredOp IntRegIndex _op1) : PredOp(mnem, _machInst, __opClass), op1(_op1) {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with a register @@ -113,6 +116,8 @@ class BranchRegReg : public PredOp IntRegIndex _op1, IntRegIndex _op2) : PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Branch to a target computed with an immediate and a register |