diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/arm/insts/data64.cc | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/arm/insts/data64.cc')
| -rw-r--r-- | src/arch/arm/insts/data64.cc | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc index f65219870..2f4dc117b 100644 --- a/src/arch/arm/insts/data64.cc +++ b/src/arch/arm/insts/data64.cc @@ -56,7 +56,7 @@ DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", #%d", imm); return ss.str(); } @@ -84,9 +84,9 @@ DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); return ss.str(); } @@ -95,9 +95,9 @@ DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", #%d", imm); return ss.str(); } @@ -107,9 +107,9 @@ DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", #%d, #%d", imm1, imm2); return ss.str(); } @@ -119,11 +119,11 @@ DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); - printReg(ss, op2); + printIntReg(ss, op2); return ss.str(); } @@ -132,11 +132,11 @@ DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); - printReg(ss, op2); + printIntReg(ss, op2); ccprintf(ss, ", #%d", imm); return ss.str(); } @@ -146,13 +146,13 @@ DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); - printReg(ss, op2); + printIntReg(ss, op2); ccprintf(ss, ", "); - printReg(ss, op3); + printIntReg(ss, op3); return ss.str(); } @@ -162,7 +162,7 @@ DataXCondCompImmOp::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", #%d, #%d", imm, defCc); ccprintf(ss, ", "); printCondition(ss, condCode, true); @@ -175,9 +175,9 @@ DataXCondCompRegOp::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); - printReg(ss, op2); + printIntReg(ss, op2); ccprintf(ss, ", #%d", defCc); ccprintf(ss, ", "); printCondition(ss, condCode, true); @@ -190,11 +190,11 @@ DataXCondSelOp::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, dest); + printIntReg(ss, dest); ccprintf(ss, ", "); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); - printReg(ss, op2); + printIntReg(ss, op2); ccprintf(ss, ", "); printCondition(ss, condCode, true); return ss.str(); |