diff options
author | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
---|---|---|
committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-03-17 19:20:19 -0500 |
commit | 031f396c71e750fede19651ba3a14e262a87e117 (patch) | |
tree | bfd6520d87f36775200aff930b632bfe3c80af1e /src/arch/arm/insts/macromem.cc | |
parent | e65f480d62e0112e89af6130e2f2024d89417df0 (diff) | |
download | gem5-031f396c71e750fede19651ba3a14e262a87e117.tar.xz |
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:
URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.
Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
Diffstat (limited to 'src/arch/arm/insts/macromem.cc')
-rw-r--r-- | src/arch/arm/insts/macromem.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 2a45cf2e6..c03b7ccc1 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -896,6 +896,15 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + ss << "[PC,CPSR]"; + return ss.str(); +} + +std::string MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; |