diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/arm/insts/macromem.cc | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/arm/insts/macromem.cc')
| -rw-r--r-- | src/arch/arm/insts/macromem.cc | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index 9a3e70616..591f9fd79 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -1525,9 +1525,9 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, ura); + printIntReg(ss, ura); ss << ", "; - printReg(ss, urb); + printIntReg(ss, urb); ss << ", "; ccprintf(ss, "#%d", imm); return ss.str(); @@ -1538,9 +1538,9 @@ MicroIntImmXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, ura); + printIntReg(ss, ura); ss << ", "; - printReg(ss, urb); + printIntReg(ss, urb); ss << ", "; ccprintf(ss, "#%d", imm); return ss.str(); @@ -1560,9 +1560,9 @@ MicroIntRegXOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, ura); + printIntReg(ss, ura); ccprintf(ss, ", "); - printReg(ss, urb); + printIntReg(ss, urb); printExtendOperand(false, ss, (IntRegIndex)urc, type, shiftAmt); return ss.str(); } @@ -1572,9 +1572,9 @@ MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, ura); + printIntReg(ss, ura); ss << ", "; - printReg(ss, urb); + printIntReg(ss, urb); return ss.str(); } @@ -1583,11 +1583,11 @@ MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, ura); + printIntReg(ss, ura); ss << ", "; - printReg(ss, urb); + printIntReg(ss, urb); ss << ", "; - printReg(ss, urc); + printIntReg(ss, urc); return ss.str(); } @@ -1597,11 +1597,11 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::stringstream ss; printMnemonic(ss); if (isFloating()) - printReg(ss, ura + FP_Reg_Base); + printFloatReg(ss, ura); else - printReg(ss, ura); + printIntReg(ss, ura); ss << ", ["; - printReg(ss, urb); + printIntReg(ss, urb); ss << ", "; ccprintf(ss, "#%d", imm); ss << "]"; @@ -1613,11 +1613,11 @@ MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printReg(ss, dest); + printIntReg(ss, dest); ss << ","; - printReg(ss, dest2); + printIntReg(ss, dest2); ss << ", ["; - printReg(ss, urb); + printIntReg(ss, urb); ss << ", "; ccprintf(ss, "#%d", imm); ss << "]"; |