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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-19 11:45:03 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-10 10:15:05 +0000 |
| commit | 90e524ba193ab5e867a8098a814f8dbb31aeee26 (patch) | |
| tree | 56bce33f2d49c01b1f879638202a067e5d65e718 /src/arch/arm/insts/macromem.cc | |
| parent | f191901bd8def842b4f8c9d06f4adc0f47ae4918 (diff) | |
| download | gem5-90e524ba193ab5e867a8098a814f8dbb31aeee26.tar.xz | |
arch-arm: Disambuiguate NumFloatV7ArchRegs usage
Sometimes NumFloatV7ArchRegs is used to specify the maximum number of
AArch32 floating point registers. Sometimes it is just used for indexing
a free register storage to be used by microcode. In that scenario,
VecSpecialElem should be used, which is a index to the first available
non architectural register for floating point.
Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/insts/macromem.cc')
| -rw-r--r-- | src/arch/arm/insts/macromem.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index e6de8321d..bff0d3e72 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -472,7 +472,7 @@ VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, if (deinterleave) numMicroops += (regs / elems); microOps = new StaticInstPtr[numMicroops]; - RegIndex rMid = deinterleave ? NumFloatV7ArchRegs : vd * 2; + RegIndex rMid = deinterleave ? VecSpecialElem : vd * 2; uint32_t noAlign = TLB::MustBeOne; @@ -575,7 +575,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, numMicroops += (regs / elems); microOps = new StaticInstPtr[numMicroops]; - RegIndex ufp0 = NumFloatV7ArchRegs; + RegIndex ufp0 = VecSpecialElem; unsigned uopIdx = 0; switch (loadSize) { @@ -837,7 +837,7 @@ VstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t noAlign = TLB::MustBeOne; - RegIndex rMid = interleave ? NumFloatV7ArchRegs : vd * 2; + RegIndex rMid = interleave ? VecSpecialElem : vd * 2; unsigned uopIdx = 0; if (interleave) { @@ -939,7 +939,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, numMicroops += (regs / elems); microOps = new StaticInstPtr[numMicroops]; - RegIndex ufp0 = NumFloatV7ArchRegs; + RegIndex ufp0 = VecSpecialElem; unsigned uopIdx = 0; switch (elems) { |