diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:12 -0500 |
commit | 1fcd389fa327493d66767ee11698ccff8fccb7ac (patch) | |
tree | d7ebff3689093d76e1339b674ebf7d507d2e6de4 /src/arch/arm/insts/macromem.hh | |
parent | 67766cbf17451559207d072eaf4fc6fb589a2656 (diff) | |
download | gem5-1fcd389fa327493d66767ee11698ccff8fccb7ac.tar.xz |
ARM: Make sure macroops aren't interrupted midinstruction.
Do this by setting the delayed commit flag for all but the last microop.
Diffstat (limited to 'src/arch/arm/insts/macromem.hh')
-rw-r--r-- | src/arch/arm/insts/macromem.hh | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 436a5b4a3..25d0ab734 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -60,10 +60,26 @@ number_of_ones(int32_t val) return ones; } +class MicroOp : public PredOp +{ + protected: + MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) + : PredOp(mnem, machInst, __opClass) + { + } + + public: + void + setDelayedCommit() + { + flags[IsDelayedCommit] = true; + } +}; + /** * Microops of the form IntRegA = IntRegB op Imm */ -class MicroIntOp : public PredOp +class MicroIntOp : public MicroOp { protected: RegIndex ura, urb; @@ -71,7 +87,7 @@ class MicroIntOp : public PredOp MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, uint8_t _imm) - : PredOp(mnem, machInst, __opClass), + : MicroOp(mnem, machInst, __opClass), ura(_ura), urb(_urb), imm(_imm) { } |