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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
| commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
| tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /src/arch/arm/insts/macromem.hh | |
| parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
| parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
| download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz | |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'src/arch/arm/insts/macromem.hh')
| -rw-r--r-- | src/arch/arm/insts/macromem.hh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 1a2db8b9a..4933a1e7c 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -134,6 +134,27 @@ class MicroNeonMixLaneOp : public MicroNeonMixOp { } }; + +/** + * Microops of the form + * PC = IntRegA + * CPSR = IntRegB + */ +class MicroSetPCCPSR : public MicroOp +{ + protected: + IntRegIndex ura, urb, urc; + + MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, + IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) + : MicroOp(mnem, machInst, __opClass), + ura(_ura), urb(_urb), urc(_urc) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + /** * Microops of the form IntRegA = IntRegB */ |