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authorGabe Black <gblack@eecs.umich.edu>2010-08-25 19:10:42 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-08-25 19:10:42 -0500
commit6368edb281f162e4fbb0a91744992a25134135f4 (patch)
treee84dfa7d10903e6c7a56e01cc6ca23f4b0d41908 /src/arch/arm/insts/macromem.hh
parentf4f6b31df1a8787a12d71108eac24543bdf541e3 (diff)
downloadgem5-6368edb281f162e4fbb0a91744992a25134135f4.tar.xz
ARM: Implement all ARM SIMD instructions.
Diffstat (limited to 'src/arch/arm/insts/macromem.hh')
-rw-r--r--src/arch/arm/insts/macromem.hh118
1 files changed, 113 insertions, 5 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 003f5a3fd..923e9c0a1 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -80,16 +80,66 @@ class MicroOp : public PredOp
};
/**
+ * Microops for Neon loads/stores
+ */
+class MicroNeonMemOp : public MicroOp
+{
+ protected:
+ RegIndex dest, ura;
+ uint32_t imm;
+ unsigned memAccessFlags;
+
+ MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _dest, RegIndex _ura, uint32_t _imm)
+ : MicroOp(mnem, machInst, __opClass),
+ dest(_dest), ura(_ura), imm(_imm),
+ memAccessFlags(TLB::MustBeOne)
+ {
+ }
+};
+
+/**
+ * Microops for Neon load/store (de)interleaving
+ */
+class MicroNeonMixOp : public MicroOp
+{
+ protected:
+ RegIndex dest, op1;
+ uint32_t step;
+
+ MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _dest, RegIndex _op1, uint32_t _step)
+ : MicroOp(mnem, machInst, __opClass),
+ dest(_dest), op1(_op1), step(_step)
+ {
+ }
+};
+
+class MicroNeonMixLaneOp : public MicroNeonMixOp
+{
+ protected:
+ unsigned lane;
+
+ MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ uint32_t _step, unsigned _lane)
+ : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
+ lane(_lane)
+ {
+ }
+};
+
+/**
* Microops of the form IntRegA = IntRegB op Imm
*/
-class MicroIntOp : public MicroOp
+class MicroIntImmOp : public MicroOp
{
protected:
RegIndex ura, urb;
uint8_t imm;
- MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- RegIndex _ura, RegIndex _urb, uint8_t _imm)
+ MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _ura, RegIndex _urb, uint8_t _imm)
: MicroOp(mnem, machInst, __opClass),
ura(_ura), urb(_urb), imm(_imm)
{
@@ -99,9 +149,27 @@ class MicroIntOp : public MicroOp
};
/**
+ * Microops of the form IntRegA = IntRegB op IntRegC
+ */
+class MicroIntOp : public MicroOp
+{
+ protected:
+ RegIndex ura, urb, urc;
+
+ MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _ura, RegIndex _urb, RegIndex _urc)
+ : MicroOp(mnem, machInst, __opClass),
+ ura(_ura), urb(_urb), urc(_urc)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
* Memory microops which use IntReg + Imm addressing
*/
-class MicroMemOp : public MicroIntOp
+class MicroMemOp : public MicroIntImmOp
{
protected:
bool up;
@@ -109,7 +177,7 @@ class MicroMemOp : public MicroIntOp
MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
- : MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
+ : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
{
}
@@ -129,6 +197,46 @@ class MacroMemOp : public PredMacroOp
};
/**
+ * Base classes for microcoded integer memory instructions.
+ */
+class VldMultOp : public PredMacroOp
+{
+ protected:
+ VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
+ unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
+};
+
+class VldSingleOp : public PredMacroOp
+{
+ protected:
+ VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ bool all, unsigned elems, RegIndex rn, RegIndex vd,
+ unsigned regs, unsigned inc, uint32_t size,
+ uint32_t align, RegIndex rm, unsigned lane);
+};
+
+/**
+ * Base class for microcoded integer memory instructions.
+ */
+class VstMultOp : public PredMacroOp
+{
+ protected:
+ VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
+ unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
+};
+
+class VstSingleOp : public PredMacroOp
+{
+ protected:
+ VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ bool all, unsigned elems, RegIndex rn, RegIndex vd,
+ unsigned regs, unsigned inc, uint32_t size,
+ uint32_t align, RegIndex rm, unsigned lane);
+};
+
+/**
* Base class for microcoded floating point memory instructions.
*/
class MacroVFPMemOp : public PredMacroOp